Thinned, back-illuminated, semiconductor imaging devices are advantageous over front-illuminated imagers for high fill factor and better overall efficiency of charge carrier generation and collection. A goal of the operation of such devices is for the charge carriers generated by light or other emanation incident on the backside to be driven to the front side quickly to avoid any horizontal drift, which may smear the image. It is also desirable to minimize the recombination of the generated carriers before they reach the front side, since such recombination reduces overall efficiency and sensitivity of the device.
Such desirable features may be achieved by providing a thin semiconductor layer and a high electric field within this layer. The field should extend to the back surface, so that the generated carriers, such as electrons or holes, can be driven quickly to the front side. U.S. Pat. No. 7,238,583 by Swain et. al. (the “'583 patent”), which is incorporated herein by reference in its entirety, describes a method for producing a back-illuminated imaging device that exhibits the desired internal electric field. The device of the '583 patent also employs ultra thin Silicon-on-Insulator (UTSOI) technology for providing a semiconductor substrate on which the back-illuminated imager is constructed. The practical work flow for using the method described in the '583 patent is shown in FIG. 1.
In FIG. 1, the starting structure is an initial substrate 10, sometimes referred to in the art as a UTSOI substrate. The starting UTSOI substrate 10, is composed of a mechanical substrate 12 (handle wafer) configured to provide mechanical support during processing, an insulator layer 14 (which can be, for example, a buried oxide layer of silicon (BOX)), and a semiconductor substrate 16 (also referred to as the “seed layer”). The mechanical substrate 12 may be composed of any suitable semiconductor material, such as, for example, silicon. The seed layer 16 is typically 1000-2000 A in thickness but may fall outside this range.
In Step A, the UTSOI wafer 10 is cleaned and an oxide layer 18 is grown overlying the seed layer 16 opposite the mechanical substrate 12. In Step B, the seed layer 16 is doped. Dopants are introduced into the seed layer 16 in sufficient concentration to produce a desired net doping profile. The initial net doping concentration in the seed layer 16 may be on the order of 1017 charge carriers per cubic centimeter or higher, and may be either p-type or n-type. Common dopants include boron, phosphorous, antimony, and arsenic.
In the specific case where the semiconductor is silicon, the '583 patent cites boron as the most suitable dopant for producing p-type regions. In this example, the boron dopant is incorporated within the seed layer 16 before the growth of the epitaxial layer. Although the '583 patent outlines several techniques for introducing the boron dopant, the preferred method for introduction of p-type dopants is through the use of ion-implantation. With reference to this example, in Step B, ions of boron are implanted ballistically through the oxide layer 18 into the seed layer 16 of UTSOI wafer 10.
In Step C, the UTSOI wafer 10 is cleaned and annealed in a furnace to remove the damage introduced by the ion implantation of dopants, i.e., broken bonds are reformed and dopants are incorporated at lattice sites. In Step D, the oxide layer 18 is removed and the resulting doped wafer 10′ is cleaned. In Step E, an epitaxial layer 20 is grown overlying the doped seed layer 16′, using the seed layer 16 as the template. The epitaxial layer 20 provides a layer for fabricating front side components which complete the overall imaging device. Still referring to FIG. 1, during the growth of epitaxial layer 20, dopants previously introduced into the seed layer 16 diffuse into the epitaxial layer 20 as a result of processing at or above 1000° C. At the conclusion of the growth of the epitaxial layer 20, the net doping profile is very close to the desired profile, in that at each distance from an interface 22 between the insulator layer 14 and the seed layer 16, within the seed layer 16 and epitaxial layer 20, the net carrier concentration is close to its final desired value. All remaining steps in the process are then carried out at lower temperatures, so that relatively little diffusion of dopants takes place, and the profile is essentially unchanged at the end of the process.
In Step F, once the epitaxial layer 20 is grown, with the simultaneous formation of a desired dopant profile, one or more imaging components 24 may be fabricated using known methods of semiconductor fabrication. These imaging components may include charge-coupled device (CCD) components, CMOS imaging components, photodiodes, avalanche photodiodes, phototransistors, or other optoelectronic devices, in any combination. Imaging components 24 may include both CCD and CMOS components fabricated in separate areas of the epitaxial layer 20 using known masking methods. Also included may be other electronic components such as CMOS transistors, (not shown) bipolar transistors (not shown), capacitors (not shown), or resistors (not shown). One or more p-n junctions 26 of various depths may be formed during the fabrication of the imaging components 24.
In Step G, the mechanical substrate 12 is removed. Once the fabrication of components 24 is complete, the mechanical substrate 12 is no longer needed to provide mechanical stability. Removal of the mechanical substrate 12 may also be desirable in order to allow the emanation being detected to reach the backside semiconductor. Removal of the mechanical substrate 12 may be accomplished by such methods as chemical etching, mechanical grinding, or a combination of these methods. With chemical etching, the mechanical substrate 12 may be removed selectively, without removing the insulator layer 14.
After the mechanical substrate 12 is entirely removed, the insulator layer 14 may be removed, either partially or entirely, by chemical or physical methods or a combination of the two methods. In one embodiment, the insulator layer 14 is made to act as an anti-reflection coating for electromagnetic waves having wavelengths in a predetermined range, thereby allowing more photons to reach, and be absorbed in, the semiconductor layers 16, 20. This may be accomplished by reducing thickness of the insulator layer 14 to a thickness which minimizes reflection in the predetermined wavelength range. The thickness may be determined by the wavelength range and the index of refraction of the material of the insulator layer 14 in this wavelength range.
After partially removing the insulator layer 14, one or more anti-reflective coating layers (e.g., zirconium oxide or bismuth oxide) (not shown) can be deposited on the insulation layer 14 to function as an overall anti-reflective coating stack for a desired range of wavelengths. In still other embodiments, the insulation layer 14 can be completely etched away, and one or more anti-reflective coating layers can be deposited on the seed layer 16 so as to function as an overall antireflective coating.
FIG. 2 shows a complete laminated imaging device 28 as described in the '583 patent, with an anti-reflection coating 30. For thin devices, a sufficiently rigid lamination layer 32 may be added to provide mechanical stability. In FIG. 2, the lamination layer 32 is shown on the front side of the imaging device 28. Lamination layer 32 may be bonded to the front side of the wafer with cement after concluding the fabrication of the imaging components 24 and other front-side components. Alternatively, the lamination layer may be bonded to the back of the imaging device 28. If the lamination layer 32 is bonded to the back of the imaging device 28, lamination layer material, any cement used to bond the lamination layer, and any other materials between the lamination layer 32 and the back of the device 28 must be transparent to, and not degraded by, detected radiation.
Referring again to FIG. 1, a goal of the process for manufacturing a back-illuminated imaging device described in the '583 patent is the creation of a final net dopant concentration profile in the seed layer 16 and the epitaxial layer 20 which has a maximum value at the interface 22 between the seed layer 16 and the insulator layer 14. The final net dopant concentration profile after the epitaxial growth (i.e., Step E) decreases monotonically with increasing distance from the interface 22 within a portion of the seed layer 16 and the epitaxial layer 20 between the interface 22 and the p-n junctions 26 shown in FIG. 1 (p-n junctions 26 are created during fabrication of the front-side components 24). Such a profile may give rise to an electric field within the seed layer 16 and the epitaxial layer 20 tending to drive photo-generated electrons toward the front side imaging components 24 and minimizing the trapping of these electrons near the backside.
Processing parameters such as doping levels, initial doping profiles, and temperatures are chosen to give the desired doping profile, as described above. FIGS. 3 through 5, reproduced from the '583 patent, show the results of computer simulations of desired net doping profiles. In these figures, various regions correspond to regions of the structures shown in FIG. 1, as follows:
Region 150 corresponds to the mechanical substrate 12; Region 130 corresponds to the insulator layer 14 comprising an oxide of silicon; Region 120 corresponds to the seed layer 16 comprising silicon; Region 100 corresponds to the epitaxial layer 20 comprising silicon; reference number 125 corresponds to the interface 22 between the seed layer 16 and the insulator layer 14; and reference number 110 corresponds to an interface between the seed layer 16 and the epitaxial layer 20.
FIG. 3 shows an initial doping profile 135 in seed layer 120, before growth of the epitaxial layer 100. Boron is used as the dopant, and it may be introduced into the seed layer 120 by any of the methods for introducing dopants described above. Initial profile 135 is created by boron doping (or, equivalently, net p-type doping) with a net p-type concentration of about 1×1019 carriers per cubic centimeter, assumed uniform through the seed layer 120.
FIG. 4 shows a net final doping profile 140 after growth of the epitaxial layer 100. The net final doping profile 140 in this embodiment is p-type; alternatively it could be n-type. Boron atoms starting in the seed layer 120 diffuse into the epitaxial layer 100 during growth of that layer to produce the net doping profile 140, as discussed above. The net final doping profile 140 in this simulated process exhibits the following desirable features: it has a maximum value at the interface 125 between the seed layer 120 and the insulator layer 130 and decreases monotonically with increasing distance from the interface 125 within the seed layer 120 and the epitaxial layer 100. The net final doping profile 140 has a “dual” slope which decreases monotonically from the interface 125 at a first average rate, and decreases monotonically at a second average rate substantially in the region 140 that is slower than the first average rate substantially within the region 120 (i.e., the seed layer 120).
FIG. 5 shows the same doping profile as FIG. 4 on a larger scale of distance, in order to show essentially the entire profile. At some distance from the interface 125, the monotonically decreasing portion of the net final doping profile 140 meets the background doping level 145 in the epitaxial layer 100. The doping level remains at this concentration level 145 all the way to the junctions (not shown in FIG. 5). As long as net doping concentration 140, 145 does not increase with distance away from the interface 125, carriers generated in the seed layer 120 or the epitaxial layer 100 by waves or particles incident on the backside may tend to be driven toward the front imaging components (not shown) and not in the opposite direction.
One of the concerns expressed about high-resolution imaging devices made using technology that is similar to that disclosed in the '583 patent is the potential presence of dark current in the resulting imager. Dark current is the generation of carriers (electrons or holes), exhibited by a back-illuminated imager during periods when the imager is not actively being exposed to light. Dark current is detrimental to back-illuminated imager operation because excess dark current signal collected along with a desired optically generated signal results in higher levels of fixed pattern and excess random shot noise. The offset signal produced by dark current is seen as a non-uniform shading in a displayed image.
A solution to the dark current problem is described in U.S. patent application Ser. No. 11/752,601, filed on May 23, 2007 by Levine et. al. (the “'601 application”), which is a continuation-in-part of the '583 patent, and is incorporated herein by reference in its entirety. Referring now to FIG. 6, which is reproduced from FIG. 7 of the '601 application, there is shown a desired net doping profile 172 for a back-illuminated imaging sensor fabricated on Silicon-on-Insulator (SOI) which is designed for the reduction of dark current. Unlike the doping profiles shown in FIGS. 3-5, the net doping profile of FIG. 6 has a peak 190 a predetermined distance from the interface 180 between the insulating (buried oxide) layer 165 and the seed layer 170 (inside the region 170). The doping level, which can be p-type or n-type, increases monotonically beginning at the interface 180 between the insulator layer 165 and the seed layer 170. The doping profile continues to increase monotonically in the region 185, known as the dead band, until reaching a peak 190 within the seed layer 170 before monotonically decreasing, shown by the curve 195 inside the regions 170, 175 corresponding to one or both of the seed layer 16 and the epitaxial layer 20 of FIG. 1. The desired net doping profile 172 can be approximately Gaussian in shape.
Both dark current electrons and signal electrons can be influenced by the dead band-generated electric field. Processing parameters and the range of wavelength of operation are chosen to allow signal electrons to pass the dead band peak 190 toward the front side imaging components 24 while preventing dark current electrons from penetrating this barrier. The potential barrier corresponding to the doping maximum 190 should be large enough to prevent thermionic emission of dark current from moving past the doping peak 190 into the regions 170, 175. To assure negligible thermionic emission of dark current electrons over the potential barrier peak 190, the barrier peak voltage level in a preferred embodiment is about 10 times greater than kT, but may range from about 3 to 30 times greater than kT, where k is the Botzmann constant and T is absolute temperature in Kelvins. For signal electrons to get past the barrier peak 190, the absorption depth of incident signal photons, which depends on their wavelength, needs to be greater than the distance of the peak 190 from the interface 180 between the seed layer 170 and the insulator layer 165.
The dead band can be created by ion-implantation method previously described in FIG. 1, or by custom doping during epitaxial growth on a seed layer 16. In FIG. 6, instead of growing a second oxide layer overlying the seed layer 170 and then performing ion implantation through the second oxide layer, the dead band profile 172 can be obtained by growing an epitaxial layer 175 directly on the seed layer 170 and varying the doping concentration appropriately, as can be appreciated by those skilled in the art.
The methods for manufacturing a back illuminated imager based on either of the '583 patent or the Levine et al. '601 application requires several cleaning steps, which may leave residue on the ultra thin silicon surface. Residue is undesirable because it can result in unwanted image artifacts. Accordingly, what would be desirable, but has not yet been provided, is a method for producing imagers with improved characteristics and fewer processing (e.g., cleaning) steps as compared to prior art devices.